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[VHDL-FPGA-Verilog] plj

Description: 这是一个基于可编程逻辑器件的程序，用来实现自动转换量程频率计控制器，该程序在可以再仿真器上仿真实现-This is a programmable logic device based on the procedures used to automatically convert the frequency range of the controller, the program can be in the simulation simulator
Platform: | Size: 176128 | Author: jyb | Hits:

[Other] EDAkechengsheji

Description: 实现6位频率计，防止数据溢出，并对频率进行三分频-Frequency to achieve 6 to prevent data overflow, and one-third of the frequency band
Platform: | Size: 207872 | Author: fengin | Hits:

[VHDL-FPGA-Verilog] 4_31

Description: 这是一个交织器/解交织器的FPGA实现，虽然交织器的功能简单，但是其实现比较复杂-This is an interleaver/de-interleaver to achieve the FPGA, although the function of interleaver simple, but its more complicated to achieve
Platform: | Size: 834560 | Author: 谢建伟 | Hits:

[VHDL-FPGA-Verilog] OCM12864

Description: 含有12864LCD 的正确使用方法，以及指令的设置-12864LCD contain the proper use of methods, as well as set up commands
Platform: | Size: 915456 | Author: ghost | Hits:

[Communication-Mobile] encode_finish

Description: Turbo码编码器的encode最上层模块，它的主要作用是连接Turbo码编码器的其他模块-Turbo code encoder encode top-level module, its main role is to connect the Turbo Code encoder other modules
Platform: | Size: 1024 | Author: sunhao | Hits:

[VHDL-FPGA-Verilog] 15-IP-core

Description: 15个免费的IP核 IP核源代码 -15 IP cores
Platform: | Size: 4579328 | Author: chris | Hits:

[Embeded-SCM Develop] FPGA-PCI

Description: 基于FPGA的PCI接口源代码及Testbench Verilog程序代码-fpag pci
Platform: | Size: 467968 | Author: lang | Hits:

[Books] fpga_Question

Description: FPGA的常见小问题锦集，也许困扰你已久的问题答案就在其中-FPGA problems, perhaps problems you have the answer long-standing problem in which ~ ~ ~
Platform: | Size: 41984 | Author: lishuang | Hits:

[VHDL-FPGA-Verilog] xapp460

Description: 利用FPGA实现TMDS接口标准，可用于DVI以及HDMI接口的FPGA实现（含文档）-Video Connectivity Using TMDS I/O in Spartan-3A FPGAs
Platform: | Size: 1594368 | Author: wicky | Hits:

[VHDL-FPGA-Verilog] verilog_pli

Description: pli函数在verilog中大量应用，但介绍pli的资料并不多，压缩包中的文档是我搜集的pli的资料，希望有对你有帮助。-Pli system fuction is used in verilog language, but material related pli in domestic is rare. the rar package is my collection on pli , hop it is useful.:)
Platform: | Size: 2228224 | Author: jhv | Hits:

[Other] a

Description: 详细的讲述了数字示波器的制作方法，参数能达到200MHz，波形失真率很低-Detail the production of digital oscilloscope method, parameters to achieve 200MHz, low waveform distortion rate
Platform: | Size: 1897472 | Author: 雄鹰 | Hits:

[VHDL-FPGA-Verilog] dengjingdu

Description: 根据第三届（1997年）全国大学生电子设计竞赛题目：简易数字频率计，完全用FPGA芯片做的一个等精度数字频率计。-According to the third (1997) National Undergraduate Electronic Design Contest Topic: simple digital frequency meter, complete with a FPGA chip, such as doing precision digital frequency meter.
Platform: | Size: 3051520 | Author: song | Hits:

[Books] ModelGuide

Description: VHDL Modelling Guidelines Approved by R. Creasey R. Coirault Onboard Data Division Radio Frequency Systems Division Prepared by P. Sinander
Platform: | Size: 92160 | Author: suhasan | Hits:

[USB develop] pci-verilog

Description: USB及PCI总线设计的一些源代码（经测试）-USB and PCI bus design some of the source code
Platform: | Size: 431104 | Author: tom | Hits:

[Embeded-SCM Develop] 1

Description: Avalon总线的pwm定制，在niosII下定制了PWM通过avalon总线链接到niosII上，绝非一般的实验，应用在实际的工控项目中。-Avalon bus pwm custom, under the custom of the PWM in the niosII by avalon bus link to niosII on the experiment in general not applied in real industrial control projects.
Platform: | Size: 584704 | Author: 陈泸华 | Hits:

[VHDL-FPGA-Verilog] c_xapp454

Description: 这是xilinx应用指南xapp454的中文版本。本应用指南说明与 Micron DDR2 SDRAM 器件连接时，Spartan™ -3 器件中 DDR2 SDRAM 存储器接口的实现。本文档先简单介绍了 DDR2 SDRAM 器件的特性，然后对 DDR2 SDRAM 存储器接口的实现进行了详细说明。-This is the xilinx application note xapp454 the Chinese version. This application note and the Micron DDR2 SDRAM device is connected, Spartan ™ -3 devices DDR2 SDRAM memory interface implementation. This document briefly describes the DDR2 SDRAM device features, and then the realization of DDR2 SDRAM memory interface is described in detail.
Platform: | Size: 217088 | Author: 陈阳 | Hits:

[VHDL-FPGA-Verilog] c_xapp851

Description: 这是xilinx应用指南xapp851的中文版本。本应用指南描述了在 Virtex™ -5 器件中实现的 200 MHz DDR SDRAM （JEDEC DDR400 (PC3200) 标准）控制器。本设计实现使用 IDELAY 单元调整读数据时序。读数据时序校准和调整在此控制器中完成。-This is the xilinx application note xapp851 the Chinese version. This application note describes the Virtex ™ -5 devices to achieve 200 MHz DDR SDRAM (JEDEC DDR400 (PC3200) standard) controller. The Design and Implementation of the use of IDELAY unit to adjust read data timing. Reading the data calibration and adjust the timing for completion of this controller.
Platform: | Size: 408576 | Author: 陈阳 | Hits:

[Embeded-SCM Develop] DW8051

Description: 8051Ip核内部ram。很多8051iP核都没有内部ram，上传一个希望对大家有用-internel ram of 8051Ip
Platform: | Size: 73728 | Author: 刘超 | Hits:

[Windows Develop] juanjicoder

Description: 卷积码是一种性能优良的差错控制编码。本文在阐述卷积码编解码器基本工作原理的基础上, 提出了在MAX+ P lusÊ 开发平台上基于VHDL 语言设计(2, 1, 6) 卷积码编解码器的方法。仿真实验结果表明了该编解码器的正确性和合 理性。-juanjicoder
Platform: | Size: 176128 | Author: 徐军 | Hits:

[VHDL-FPGA-Verilog] 5b6b

Description: 5B6B码是光纤数字通信系统中使用比较广泛的一种线路码型! 数据经过5B6B编码和并串转换后在光纤上传输，串行码序列中连续的比特0或比特1的长度不超过5，数据在0和1之间变换的密度很高,并具有直流平衡的特性，有利于接收电路和时钟恢复电路的设计。-5B6B code is used in fiber optic digital communication systems a more extensive line pattern! Data are 5B6B encoding and conversion, and string after the fiber transmission, serial code sequences in continuous bit 0 or bit 1 of the length of not more than 5, data between 0 and 1, the high density of transformation, and has the characteristics of DC balance, favorable reception circuit and clock recovery circuit.
Platform: | Size: 3072 | Author: 王彬 | Hits:
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